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GS73024AB
ns 3.3 V VDD VDD and VSS
Commercial Temp Industrial Temp Features
Asynchronous SRAM
119-Bump Ball Grid Array Package
* Fast access time: 8, 10, 12 ns * CMOS low power operation: 250/200/170 mA at minimum cycle time * Single 3.3 V 0.3V power supply * All inputs and outputs are TTL-compatible * Fully static operation * Industrial Temperature Option: -40 to 85C * Package B: 14 mm x 22 mm, 119-bump, 1.27mm pitch BGA
Description
The GS73024A is a high speed CMOS Static RAM organized as 131,072 words by 24 bits. Static design eliminates the need for external clocks or timing strobes. Operating on a single 3.3 V power supply, and all inputs and outputs are TTL-compatible. The GS73024A is available in a 119-bump BGA package.
Block Diagram
A0 Address Input A16
CE
Row Decoder
Memory Array
Column Decoder
Control WE OE
I/O Buffer DQ1 DQ24
Pin Descriptions Symbol
A0 to A16 WE CE VDD
Description
Address input Write enable input Chip enable input +3.3 V power supply
Symbol
DQ1 to DQ24 OE VSS
Description
Data input/output Output enable input Ground
Rev: 1.03 12/2005
1/12
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS73024AB
119-Bump, 1.27 mm Pitch BGA Pad Out--Top View (Package B)
1 A B C D E F G H J K L M N P R T U NC NC DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 VDD DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 NC NC
2 A3 A7 NC VDD NC VDD NC VDD VSS VDD NC VDD NC VDD NC A11 A15
3 A2 A6 NC VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A10 A14
4 A16 CE NC VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC WE OE
5 A1 A5 NC VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS NC A9 A13
6 A0 A4 NC VDD NC VDD NC VDD VSS VDD NC VDD NC VDD NC A8 A12
7 NC NC DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 VDD DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 NC NC
Rev: 1.03 12/2005
2/12
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS73024AB
Truth Table
CE H L L L X: "H" or "L" OE X L X H WE X H L H Mode Not selected Read Write Output disable DQ0 to DQ23 High Z Data Out Data In High Z IDD VDD Current ISB1, ISB2
Absolute Maximum Ratings Parameter
Supply Voltage Input Voltage Output Voltage Allowable BGA power dissipation Storage temperature
Symbol
VDD VIN VOUT PD TSTG
Rating
-0.5 to +4.6 -0.5 to VDD +0.5 ( 4.6 V max.) -0.5 to VDD +0.5 ( 4.6 V max.) 1.5 -55 to 150
Unit
V V V W
oC
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Rev: 1.03 12/2005
3/12
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS73024AB
Recommended Operating Conditions Parameter
Supply Voltage for -10/12 Supply Voltage for -8 Input High Voltage Input Low Voltage Ambient Temperature, Commercial Range Ambient Temperature, Industrial Range
Symbol
VDD VDD VIH VIL TAc TAi
Min
3.0 3.135 2.0 -0.3 0 -40
Typ
3.3 3.3 -- -- -- --
Max
3.6 3.6 VDD+0.3 0.8 70 85
Unit
V V V V
o
C C
o
Notes: 1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than -2 V and not exceed 20 ns.
Capacitance Parameter
Input Capacitance I/O Capacitance
Symbol
CIN COUT
Test Condition
VIN = 0 V VOUT = 0 V
Max
5 7
Unit
pF pF
Notes: 1. Tested at TA = 25C, f = 1 MHz 2. These parameters are sampled and are not 100% tested.
DC I/O Pin Characteristics Parameter
Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
Symbol
IIL IOL VOH VOL
Test Conditions
VIN = 0 to VDD Output High Z, VOUT = 0 to VDD IOH = -4 mA IOL = +4 mA
Min
-1 uA -1 uA 2.4 --
Max
1 uA 1 uA -- 0.4 V
Rev: 1.03 12/2005
4/12
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS73024AB
AC Test Conditions Parameter
Input high level Input low level Input rise time Input fall time Input reference level Output reference level Output load
Conditions
VIH = 2.4 V VIL = 0.4 V t = 1 V/ns tf = 1 V/ns 1.4 V 1.4 V Fig. 1& 2
Output Load 1
DQ 50 VT = 1.4 V 30pF1
Output Load 2
3.3 V DQ 5pF1 589 434
Notes: 1. Includes scope and jig capacitance 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
Power Supply Currents Parameter Symbol Test Conditions
CE VIL All other inputs VIH or VIL Min. cycle time IOUT = 0 mA CE VIH All other inputs VIH or VIL Min. cycle time CE VDD - 0.2V All other inputs VDD - 0.2V or 0.2V
0 to 70C 8 ns 10 ns 12 ns 8 ns
-40 to 85C 10 ns 12 ns
Operating Supply Current
IDD
250 mA
200 mA
170 mA
260 mA
210 mA
180 mA
Standby Current
ISB1
40 mA
40 mA
30 mA
50 mA
50 mA
40 mA
Standby Current
ISB2
10 mA
20 mA
Rev: 1.03 12/2005
5/12
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS73024AB
AC Characteristics Read Cycle Parameter
Read cycle time Address access time Chip enable access time (CE) MUX control to output valid (V/S) Output enable to output valid (OE) Output hold from address change Output hold from MUX controls change Chip enable to output in low Z (CE) Output enable to output in low Z (OE) Chip disable to output in High Z (CE) Output disable to output in High Z (OE) * These parameters are sampled and are not 100% tested
Symbol
tRC tAA tAC tAV tOE tOH tOH1 tLZ* tOLZ* tHZ* tOHZ*
-8 Min
8 -- -- -- -- 3 3 3 0 -- --
-10 Max
-- 8 8 8 4 -- -- -- -- 4 4
-12 Max
-- 10 10 10 5 -- -- -- -- 5 5
Min
10 -- -- -- -- 3 3 3 0 -- --
Min
12 -- -- -- -- 3 3 3 0 -- --
Max
-- 12 12 12 6 -- -- -- -- 6 6
Unit
ns ns ns ns ns ns ns ns ns ns ns
Read Cycle 1: CE = OE = VIL, WE = VIH
tRC Address tAA tOH Data Out Previous Data Data valid
Rev: 1.03 12/2005
6/12
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS73024AB
Read Cycle 2: WE = VIH
tRC Address tAA CE tAC tLZ OE tOLZ High impedance tOE
Data valid
tHZ
tOHZ
Data Out
Write Cycle Parameter
Write cycle time Address valid to end of write Chip enable to end of write (CE) Data set up time Data hold time Write pulse width Address set up time Write recovery time (WE) Write recovery time ( CE ) Output Low Z from end of write Write to output in High Z * These parameters are sampled and are not 100% tested
Symbol
tWC tAW tCW tDW tDH tWP tAS tWR tWR1 tWLZ* tWHZ*
-8 Min
8 5.5 5.5 4 0 5.5 0 0 0 2 --
-10 Max
-- -- -- -- -- -- -- -- -- -- 4
-12 Max
-- -- -- -- -- -- -- -- -- -- 5
Min
10 7 7 5 0 7 0 0 0 3 --
Min
12 8 8 6 0 8 0 0 0 3 --
Max
-- -- -- -- -- -- -- -- -- -- 6
Unit
ns ns ns ns ns ns ns ns ns ns ns
Rev: 1.03 12/2005
7/12
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS73024AB
Write Cycle 1: WE control
tWC Address tAW OE tCW CE tAS WE tDW Data In tWHZ Data Out
High impedance Data valid
tWR
tWP tDH
tWLZ
Write Cycle 2: CE control
tWC Address tAW OE tAS CE WE tWP tDW Data In Data Out
Data valid
tWR1 tCW
tDH
High impedance
Rev: 1.03 12/2005
8/12
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS73024AB
Package Dimensions--119-Bump FPBGA (Package B, Variation 1) (Date Code: yyww.31)
Pin #1 Corner
BOTTOM VIEW A1 O0.10S C O0.30S C AS B S O0.60~0.90 (119x)
1 2 3 45 6 7
A B C D E F G H J K L M N P R T U
O1.00(3x) REF
7 6 5 43 2 1
A B C D E F G H J K L M N P R T U
220.20
19.50
0.70 REF
12.00
B 1.27 7.62 A 0.20(4x) 140.20
0.900.10 0.15 C
0.560.05
Rev: 1.03 12/2005
0.50~0.70 2.06.0.13
C
SEATING PLANE
0.15 C
30 TYP.
9/12
20.32
1.27
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS73024AB
Package Dimensions--119-Bump FPBGA (Package B, Variation 2) (Date Code: yyww.3H)
A1 1
A B C D E F G H J K L M N P R T U
TOP VIEW
BOTTOM VIEW A1 O0.10S C O0.30S C AS B S O0.60~0.90 (119x)
2
3
4
5
6
7
7 6 5 43 2 1
A B C D E F G H J K L M N P R T U
220.10
B 1.27 7.62 0.15 C A 0.20(4x) 140.10
Rev: 1.03 12/2005
0.50~0.70 1.86.0.13
C
SEATING PLANE
10/12
20.32
1.27
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS73024AB
Ordering Information Part Number1
GS73024AB-8 GS73024AB-10 GS73024AB-12 GS73024AB-8I GS73024AB-10I GS73024AB-12I
Package
119-Bump BGA2 119-Bump BGA2 119-Bump BGA2 119-Bump BGA2 119-Bump BGA2 119-Bump BGA2
Access Time
8 ns 10 ns 12 ns 8 ns 10 ns 12 ns
Temp. Range
Commercial Commercial Commercial Industrial Industrial Industrial
Status
Notes: 1. Customers requiring Tape and Reel should add the character "T" to the end of the part number. For example: GS73024AB-12T. 2. Please see pages 9 and 10 for date code information for Variation 1 and Variation 2 of the 119-bump BGA.
Rev: 1.03 12/2005
11/12
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS73024AB
Revision History
Rev. Code: Old; New Types of Changes Format or Content Page/Revisions/Reason
GS73024A_r1 GS73024A_r1; GS73024A_r1_01 GS73024A_r1_01; GS73024A_r1_02 GS73024A_r1_02; GS73024A_r1_03 Content Content/Format Content
* Creation of new datasheet * Corrected pinout (balls C3, C5, R2, R3, R5, R6 changed to NC) * Corrected pin description table to reflect pinout corrections * Corrected truth table to reflect pinout corrections * Updated format * Added variation informtion to package mechanical * Added Variation 2 119 BGA to datasheet * Added date codes to mechanicals
Rev: 1.03 12/2005
12/12
(c) 2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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